Enhancement in Reliability for Multi-core system consisting of One Instruction Cores

Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of transient faults and permanent faults. The mitigation of transient faults and permanent faults at the core level has become an important design parameter in a multi-core scenario. Core level techniques is a redundancy-based fault mitigation technique that improves the lifetime reliability of multi-core systems. In an asymmetric multi-core system, the smaller cores provide fault tolerance to larger cores is a core level fault mitigation technique that has gained momentum and focus from many researchers. The paper presents an economical, asymmetric multi-core system with one instruction cores (MCSOIC). The term Hardware Cost Estimation signifies power and area estimation for MCS-OIC. In MCSOIC, OIC is a warm standby redundant core. OICs provide functional support to conventional cores for shorter periods of time. To evaluate the idea, different configurations of MCSOIC is synthesized using FPGA and ASIC. The maximum power overhead and maximum area overhead are 0.46% and 11.4% respectively. The behavior of OICs in MCS-OIC is modelled using a One-Shot System (OSS) model for reliability analysis. The model parameters namely, readiness, wakeup probability and start-up-strategy for OSS are mapped to the multi-core systems with OICs. Expressions for system reliability is derived. System reliability is estimated for special cases.Comment: 46 page

Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core Systems

Billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of faults in the circuits, and reliability issues. Existing approaches explore the usage of redundancy-based solutions for fault tolerance at core level, thread level, micro-architectural level, and software level. Core-level techniques improve the lifetime reliability of multi-core systems with asymmetric cores (large and small cores), which have gained momentum and focus among a large number of researchers. Based on the above implications, multi-core system using one instruction cores (MCS-OIC) factoring its features are proposed in this chapter. The MCS-OIC is an asymmetric multi-core architecture with MIPS core as the conventional core and OICs as the warm standby-redundant core. OIC executes only one instruction named ‘subleq _ subtract if less than or equal to zero’. When there is one of the functional units (i.e., ALU) of any conventional core fails, the opcode of the instruction is sent to the OIC. The OIC decodes the instruction opcode and emulates the faulty instruction by repeated execution of the ‘subleq’ instruction, thus providing fault tolerance. To evaluate the idea, the OIC is synthesized using ASIC and FPGA. Performance implications due to OICs at instruction and application level are evaluated. Yield analysis is estimated for various configurations of multi-core system using OICs